In applications of large scale integrations (LSIs), static random access memory (SRAM) are the widely-used on-chip memory. Unlike dynamic random access memories (DRAM), it may only need to supply power to SRAM for storing data, and it may be unnecessarily to refresh the SRAM. Therefore, SRAM may have advantages including high speed and low power consumption, etc.
FIG. 1 illustrates a circuit structure of an existing SRAM, which may have six transistors (6T SRAM). As shown in FIG. 1, the 6T SRAM may include a first pull-up PMOS transistor PU1, a second pull-up PMOS transistor PU2, a first pull-down NMOS transistor PD1 and a second pull-down NMOS transistor PD2. Sources of the first pull-up PMOS transistor PU1 and the second pull-up PMOS transistor PU2 may connect with a power source Vdd. Sources of the first pull-down NMOS transistor PD1 and the second pull-down NMOS transistor PD2 may connect with a ground Vss. The first pull-up PMOS transistor PU1 and the first pull-down NMOS transistor PD1 may form a first inverter. The second pull-up PMOS transistor PU2 and the second pull-down NMOS transistor PD2 may form a second inverter. The output of the first inverter may electrically connect with the input of the second inverter, and a first storage node Q may be formed. The input of the second inverter may electrically connect with the output of the first inverter, and a second storage node QN may be formed.
Because the first inverter and the second inverter may have a cross-coupling effect, a latch circuit may be formed. When one storage node is pulled down to a lower potential, the other storage node may be pulled up to a higher potential. The first storage node Q may connect with a first transfer gate PG1. The second storage node QN may connect with a second transfer gate PG2. The first transfer gate PG1 and the second transfer gate PG2 may connect with a word line WL.
When the word line WL is switched to a system high potential, the first transfer gate PG1 and the second transfer gate PG2 may be turned on, and a first bit line BL1 and a second bit line BL2 may be allowed to write data into the first storage node Q and the second storage node QN, or to read data from the first storage node Q and the second storage node QN. When the word line WL is switched to a system low potential, the first transfer gate PG1 and the second transfer gate PG2 may be turned off, the first bit line BL1 and the second bit line BL2 may be isolated from the first storage node Q and the second storage node QN.
However, the fabrication of the existing STRAM structures may be relatively complex. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.